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ltc3568 3568fa typical a pplica t ion fea t ures a pplica t ions descrip t ion 1.8a, 4mhz, synchronous step-down dc/dc converter the ltc ? 3568 is a constant frequency, synchronous step- down dc/dc converter. intended for medium power applications, it operates from a 2.5v to 5.5v input voltage range and has a user configurable operating frequency up to 4mhz, allowing the use of tiny, low cost capacitors and inductors 2mm or less in height. the output voltage is adjustable from 0.8v to 5v. internal sychronous 0.11 power switches with 2.4a peak current ratings provide high efficiency. the ltc3568s current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. the ltc3568 can be configured for automatic power sav- ing burst mode operation to reduce gate charge losses when the load current drops below the level required for continuous operation. for reduced noise and rf interfer- ence, the sync/mode pin can be configured to skip pulses or provide forced continuous operation. to further maximize battery life, the p-channel mosfet is turned on continuously in dropout (100% duty cycle) with a low quiescent current of 60a. in shutdown, the device draws <1a. l , lt, ltc, ltm, linear technology, the linear logo, opti-loop and burst mode are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6580258, 6304066, 6127815, 6611131. n uses tiny capacitors and inductor n high frequency operation: up to 4mhz n low r ds(on) internal switches: 0.110 n high efficiency: up to 96% n stable with ceramic capacitors n current mode operation for excellent line and load transient response n short-circuit protected n low dropout operation: 100% duty cycle n low shutdown current: i q 1a n low quiescent current: 60a n output voltages from 0.8v to 5v n selectable burst mode ? operation n sychronizable to external clock n small 3mm 3mm, 10-lead dfn package n notebook computers n digital cameras n cellular phones n handheld instruments n board mounted power supplies efficiency vs load current figure 1. step-down 1.8a regulator sync/mode v in ltc3568 pv in sw sv in pgood i th shdn/r t pgnd sgnd v fb l1 2h v out 2.5v/1.8a v in 2.5v to 5.5v 887k 412k 1000pf 3568 f01 22f + 10f 13k 22f 324k note: in dropout, the output tracks the input voltage load current (ma) efficiency (%) 100 95 90 85 80 75 70 power loss (mw) 1000 100 10 1 1 100 10000 1000 3568 ta01 10 v in = 3.3v v out = 2.5v f o = 1mhz burst mode operation efficiency power loss
ltc3568 3568fa e lec t rical c harac t eris t ics a bsolu t e maxi m u m r a t ings pv in , sv in voltages ..................................... C0.3v to 6v v fb , i th , shdn/r t voltages .......... C0.3v to (v in + 0.3v) sync/mode voltage .................... C0.3v to (v in + 0.3v) sw voltage ................................... C0.3v to (v in + 0.3v) pgood voltage ............................................ C0.3v to 6v operating junction temperature range (note 2) ............................................. C40c to 125c junction temperature (notes 5, 8) ........................ 125c storage temperature range .................. C65c to 125c (note 1) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 3.3v, r t = 324k unless otherwise specified. (note 2) symbol parameter conditions min typ max units v in operating voltage range 2.25 5.5 v i fb feedback pin input current (note 3) 0.1 a v fb feedback voltage ltc3568e (note 3) ltc3568i (note 3) l l 0.784 0.780 0.8 0.8 0.816 0.816 v v v linereg reference voltage line regulation v in = 2.25v to 5v 0.04 0.2 %/v v loadreg output voltage load regulation i th = 0.36, (note 3) i th = 0.84, (note 3) l l 0.02 C0.02 0.2 C0.2 % % g m(ea) error amplifier transconductance i th pin load = 5a (note 3) 800 s i s input dc supply current (note 4) active mode sleep mode shutdown v fb = 0.75v, sync/mode = 3.3v v sync/mode = 3.3v, v fb = 1v v shdn/rt = 3.3v 240 62 0.1 350 100 1 a a a v shdn/rt shutdown threshold high active oscillator resistor v in C 0.6 324k v in C 0.4 1m v p in c on f igura t ion top view dd package 10-lead (3mm s 3mm) plastic dfn 10 11 9 6 7 8 4 5 3 2 1 i th v fb pgood sv in pv in shdn/r t sync/mode sgnd sw pgnd t jmax = 125c, ja = 43c/w, jc = 3c/w exposed pad (pin 11) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3568edd#pbf ltc3568edd#trpbf lcsg 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3568idd#pbf ltc3568idd#trpbf lcsg 10-lead (3mm 3mm) plastic dfn C40c to 125c lead based finish tape and reel part marking* package description temperature range ltc3568edd ltc3568edd#tr lcsg 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3568idd ltc3568idd#tr lcsg 10-lead (3mm 3mm) plastic dfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc3568 3568fa f osc oscillator frequency r t = 324k (note 7) 0.85 1 1.15 4 mhz mhz f sync synchronization frequency (note 7) 0.4 4 mhz i lim peak switch current limit i th = 1.3 2.4 3 4 a r ds(on) top switch on-resistance (note 6) v in = 3.3v 0.11 0.15 bottom switch on-resistance (note 6) v in = 3.3v 0.11 0.15 i sw(lkg) switch leakage current v in = 6v, v ith/run = 0v, v fb = 0v 0.01 1 a v uvlo undervoltage lockout threshold v in ramping down 2 2.25 v pgood power good threshold v fb ramping up, shdn/r t = 1v v fb ramping down, shdn/r t = 1v 6.8 C7.6 % % rpgood power good pull-down on-resistance 118 200 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 3.3v, r t = 324k unless otherwise specified. (note 2) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3568 is tested under pulsed load conditions such that t j = t a . the ltc3568e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3568i is guaranteed over the full C40c to 125c operating junction temperature range. the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistors and other environmental factors. note 3: the ltc3568 is tested in a feedback loop which servos v fb to the midpoint for the error amplifier (v ith = 0.6v). note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: t j is calculated from the ambient t a and power dissipation p d according to the following formula: t j = t a + (p d ? 43c/w) note 6: switch on-resistance is guaranteed by correlation to wafer level measurements. note 7: 4mhz operation is guaranteed by design but not production tested and is subject to duty cycle limitations (see applications information). note 8: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability.
ltc3568 3568fa v in = 3.3v v out = 2.5v i load = 100ma v out 10mv/ div i l 500ma/ div s w 2v/div 10s/div 3568 g01 v in = 3.3v v out = 2.5v i load = 100ma v out 10mv/ div i l 200ma/ div s w 2v/div 2s/div 3568 g02 v in = 3.3v v out = 2.5v i load = 100ma v out 10mv/ div i l 500ma/ div 2s/div 3568 g03 s w 2v/div typical p er f or m ance c harac t eris t ics burst mode operation pulse skipping mode forced continuous mode efficiency vs load current efficiency vs v in load step load current (ma) efficiency (%) 100 95 90 85 80 75 70 1 100 1000 10000 3568 g04 10 v in = 3.3v v out = 2.5v circuit of figure 7 burst mode operation pulse skip forced continuous 2.5 3.5 4.5 5.5 3.0 4.0 5.0 6.0 v in (v) efficiency (%) 100 95 90 85 80 75 70 65 60 3568 g05 i out = 500ma i out = 1.8a v out = 2.5v circuit of figure 7 v in = 3.3v v out = 2.5v i load = 180ma to 1.8a v out 100mv/ div i l 1a/ div 50s/div 3568 g06 1 10 100 1000 10000 load current (ma) v out error (%) 3568 g07 burst mode operation pulse skip forced continuous v in = 3.3v v out = 1.8v 0.6 0.5 0.4 0.3 0.2 0.1 ?0.4 ?0.3 ?0.2 ?0.1 0 2.0 3.0 4.0 5.0 2.5 3.5 4.5 5.5 6.0 v in (v) v out error (%) 0.20 0.15 0.10 0.05 ?0.20 ?0.15 ?0.10 ?0.05 0 3568 g08 v out = 1.8v i out = 1.8a i out = 500ma 2 3 4 5 6 v in (v) frequency variation (%) 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 3568 g09 v out = 1.8v i out = 1.25a t a = 25c load regulation line regulation frequency vs v in
ltc3568 3568fa 2.5 3 3.5 4 4.5 5 5.5 6 v in (v) r ds(on) (m) 120 115 110 105 100 95 90 3568 g12 main switch synchronous switch t a = 25c ?50 ?25 0 25 50 75 100 125 temperature (c) reference variation (%) 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 3568 g10 frequency (mhz) 0 85 efficiency (%) 90 95 100 1 2 3568 g11 3 4 v in = 3.3v v out = 2.5v i out = 500ma t a = 25c typical p er f or m ance c harac t eris t ics frequency variation vs temperature efficiency vs frequency r ds(on) vs v in r ds(on) vs temperature ?50 ?25 0 25 50 75 100 125 temperature (c) r ds(on) 160 150 140 130 120 110 100 90 80 70 60 3568 g13 v in = 3.3v v in = 2.5v v in = 5v main switch synchronous switch
ltc3568 3568fa p in func t ions shdn/r t (pin 1): combination shutdown and timing resistor pin. the oscillator frequency is programmed by connecting a resistor from this pin to ground. forcing this pin to sv in causes the device to be shut down. in shutdown all functions are disabled. sync/mode (pin 2): combination mode selection and oscillator synchronization pin. this pin controls the op- eration of the device. when tied to sv in or sgnd, burst mode operation or pulse skipping mode is selected, respectively. if this pin is held at half of sv in , the forced continuous mode is selected. the oscillation frequency can be syncronized to an external oscillator applied to this pin. when synchronized to an external clock pulse skip mode is selected. s g nd (pin 3): the signal ground pin. all small signal components and compensation components should be con- nected to this ground (see board layout considerations). sw (pin 4): the switch node connection to the inductor. this pin swings from pv in to pgnd. pgnd (pin 5): main power ground pin. connect to the (C) terminal of c out , and (C) terminal of c in . pv in (pin 6): main supply pin. must be closely decoupled to pgnd. sv in (pin 7): the signal power pin. all active circuitry is powered from this pin. must be closely decoupled to sgnd. sv in must be greater than or equal to pv in . pgood (pin 8): the power good pin. this common drain logic output is pulled to sgnd when the output voltage is not within 7.5% of regulation. v fb (pin 9): receives the feedback voltage from the ex- ternal resistive divider across the output. nominal voltage for this pin is 0.8v. i th (pin 10): error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is 0v to 1.5v. g n d (exposed pad pin 11): thermal ground. con- nect to sgnd and solder to the pcb for rated thermal performance. b lock diagra m ? + 8 9 ? + + ? ? + 0.74v 0.8v error amplifier v b burst comparator hysteresis = 80mv bclamp nmos comparator pmos current comparator reverse comparator 0.86v 5 sw 4 pgood 10 i th v fb 1 shdn/r t 2 sync/mode 3568 bd 6 pv in 3 sgnd 7 sv in slope compensation voltage reference oscillator logic i th limit ? + ? + + ? pgnd
ltc3568 3568fa o pera t ion the ltc3568 uses a constant frequency, current mode architecture. the operating frequency is determined by the value of the r t resistor or can be synchronized to an external oscillator. to suit a variety of applications, the selectable mode pin, allows the user to trade-off noise for efficiency. the output voltage is set by an external divider returned to the v fb pin. an error amplfier compares the divided output voltage with a reference voltage of 0.8v and adjusts the peak inductor current accordingly. overvoltage and undervoltage comparators will pull the pgood output low if the output voltage is not within 7.5%. main control loop during normal operation, the top power switch (p -channel mosfet) is turned on at the beginning of a clock cycle when the v fb voltage is below the the reference voltage. the current into the inductor and the load increases until the current limit is reached. the switch turns off and energy stored in the inductor flows through the bottom switch (n-channel mosfet) into the load until the next clock cycle. the peak inductor current is controlled by the voltage on the i th pin, which is the output of the error amplifier.this amplifier compares the v fb pin to the 0.8v reference. when the load current increases, the v fb voltage decreases slightly below the reference. this decrease causes the er- ror amplifier to increase the i th voltage until the average inductor current matches the new load current. the main control loop is shut down by pulling the shdn/r t pin to sv in . a digital soft-start is enabled after shutdown, which will slowly ramp the peak inductor current up over 1024 clock cycles or until the output reaches regulation, whichever is first. soft-start can be lengthened by ramping the voltage on the i th pin (see applications information section). low current operation three modes are available to control the operation of the ltc3568 at low currents. all three modes automatically switch from continuous operation to to the selected mode when the load current is low. to optimize efficiency, the burst mode operation can be selected. when the load is relatively light, the ltc3568 automatically switches into burst mode operation in which the pmos switch operates intermittently based on load demand. by running cycles periodically, the switching losses which are dominated by the gate charge losses of the power mosfets are minimized. the main control loop is interrupted when the output voltage reaches the desired regulated value. the hysteretic voltage comparator b trips when i th is below 0.24v, shutting off the switch and reducing the power. the output capacitor and the inductor supply the power to the load until i th /run exceeds 0.31v, turning on the switch and the main control loop which starts another cycle. for lower output voltage ripple at low currents, pulse skipping mode can be used. in this mode, the ltc3568 continues to switch at a constant frequency down to very low currents, where it will eventually begin skipping pulses. finally, in forced continuous mode, the inductor current is constantly cycled which creates a fixed output voltage ripple at all output current levels. this feature is desirable in telecommunications since the noise is at a constant frequency and is thus easy to filter out. another advan- tage of this mode is that the regulator is capable of both sourcing current into a load and sinking some current from the output. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. in dropout, the pmos switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. low supply operation the ltc3568 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 2v.
ltc3568 3568fa r t (k) 0 0 frequency (mhz) 0.5 1.5 2.0 2.5 1000 4.5 t a = 25c 3568 f02 1.0 500 1500 3.0 3.5 4.0 a pplica t ions i n f or m a t ion a general ltc3568 application circuit is shown in fi gure 5. external component selection is driven by the load requirement, and begins with the selection of the inductor l1. once l1 is chosen, c in and c out can be selected. operating frequency selection of the operating frequency is a tradeoff between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency, f o , of the ltc3568 is determined by an external resistor that is connected between the r t pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r f t o = ( ) ( ) ? 9 78 10 11 1 08 . ? . or can be selected using figure 2. the maximum usable operating frequency is limited by the minimum on-time and the duty cycle. this can be calculated as: f o(max) 6.67 ? (v out / v in(max) ) (mhz) the minimum frequency is limited by leakage and noise coupling due to the large resistance of r t . inductor selection although the inductor does not influence the operat- ing frequency, the inductor value has a direct effect on ripple current. the inductor ripple current i l decreases with higher inductance and increases with higher v in or v out : = ? ? ? ? ? ? ? i v f l v v l out o out in ? ? 1 accepting larger values of i l allows the use of low induc- tances, but results in higher output voltage ripple, greater core losses, and lower output current capability. a reasonable starting point for setting ripple current is i l = 0.4 ? i out , where i out is the maximum output cur- rent. the largest ripple current ?i l occurs at the maximum input voltage. to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: l v f i v v out o l out in max = ? ? ? ? ? ? ? ? ? ( ) 1 the inductor value will also have an effect on burst mode operation. the transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. figure 2. frequency vs r t inductor core selection different core materials and shapes will change the size/cur- rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar electrical char- acteristics. the choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/emi requirements than on what the ltc3568 requires to operate. table 1 shows some typical surface mount inductors that work well in ltc3568 applications.
ltc3568 3568fa a pplica t ions i n f or m a t ion table 1. representative surface mount inductors manu- facturer p a rt number value ma x dc current dcr height toko a914byw-2r2m (d52lc) 2.2h 2.05a 49m 2mm toko a915y-2r0m (d53lc-a) 2h 3.3a 22m 3mm toko a918cy-2r0m (d62lcb) 2h 2.33a 24m 2mm coilcraft d01608c-222 2.2h 2.3a 70m 3mm sumida cdrh2d18/hp1r7 1.7h 1.8a 35m 2mm sumida cdrh4d282r2 2.2h 2.04a 23m 3mm sumida cdc5d232r2 2.2h 2.16a 30m 2.5mm tdk vlcf4020t-1r8n1r9 1.8h 1.97a 46m 2mm taiyo yuden n06db2r2m 2.2h 3.2a 29m 3.2mm taiyo yuden n05db2r2m 2.2h 2.9a 32m 2.8mm cooper sd14-2r0 2h 2.37a 45m 1.45mm catch diode selection a catch diode is not necessary. input capacitor (c in ) selection in continuous mode, the input current of the converter is a square wave with a duty cycle of approximately v out /v in . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: i i v v v v rms max out in out in ? ( ) where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple cur- rent, i max = i lim C i l /2. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst case is commonly used to design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple cur- rent ratings are often based on only 2000 hours lifetime. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements of the design. an additional 0.1f to 1f ceramic capacitor is also recommended on v in for high frequency decoupling, when not using an all ceramic capacitor solution. output capacitor (c out ) selection the selection of c out is driven by the required esr to minimize voltage ripple and load step transients. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ( v out ) is determined by: + ? ? ? ? ? ? v i esr f c out l o out 1 8 where f = operating frequency, c out = output capacitance and i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since i l increases with input voltage. with i l = 0.4 ? i out the output ripple will be less than 100mv at maximum v in and f o = 1mhz with: esrc out < 130m once the esr requirements for c out have been met, the rms current rating generally far exceeds the i ripple(p-p) requirement, except for an all ceramic solution. in surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, esr or rms current handling requirement of the application. aluminum electrolytic, special polymer, ceramic and dry tantulum capacitors are all available in surface mount packages. the os-con semiconductor dielectric capacitor avail- able from sanyo has the lowest esr(size) product of any aluminum electrolytic at a somewhat higher price. special polymer capacitors, such as sanyo poscap, offer very low esr, but have a lower capacitance density than other types. tantalum capacitors have the highest capacitance density, but it has a larger esr and it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, avalable in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors have a significantly larger esr, and is often used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability.
ltc3568 0 3568fa ceramic capacitors have the lowest esr and cost but also have the lowest capacitance density, a high voltage and temperature coefficient and exhibit audible piezoelectric effects. in addition, the high q of ceramic capacitors along with trace inductance can lead to significant ringing. other capacitor types include the panasonic specialty polymer (sp) capacitors. in most cases, 0.1f to 1f of ceramic capacitors should also be placed close to the ltc3568 in parallel with the main capacitors for high frequency decoupling. ceramic input and output capacitors higher value, lower cost ceramic capacitors are now be- coming available in smaller case sizes. these are tempting for switching regulator use because of their very low esr. unfortunately, the esr is so low that it can cause loop stability problems. solid tantalum capacitor esr generates a loop zero at 5khz to 50khz that is instrumental in giving acceptable loop phase margin. ceramic capacitors remain capacitive to beyond 300khz and ususally resonate with their esl before esr becomes effective. also, ceramic caps are prone to temperature effects which requires the designer to check loop stability over the operating tem- perature range. to minimize their large temperature and voltage coefficients, only x5r or x7r ceramic capacitors should be used. a good selection of ceramic capacitors is available from taiyo yuden, tdk and murata. great care must be taken when using only ceramic input and output capacitors. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v in pin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, the ringing at the input can be large enough to damage the part. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation com- ponents and the output capacitor size. typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. the output droop, v droop , is usually about 2 to 3 times the linear drop of the first cycle. thus, a good place to start is with the output capacitor size of approximately: c i f v out out o droop 2 5. ? more capacitance may be required depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. a 22f ceramic capacitor is usually enough for these conditions. setting the output voltage the ltc3568 develops a 0.8v reference voltage between the feedback pin, v fb , and the signal ground as shown in figure 5. the output voltage is set by a resistive divider according to the following formula: v v r r out + ? ? ? ? ? ? 0 8 1 2 1 . keeping the current small (<5a) in these resistors maxi- mizes efficiency, but making them too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. to improve the frequency response, a feed-forward capaci- tor c f may also be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. shutdown and soft-start the shdn/r t pin is a dual purpose pin that sets the oscil- lator frequency and provides a means to shut down the ltc3568. this pin can be interfaced with control logic in several ways, as shown in figure 3(a) and figure 3(b). the i th pin is primarily for loop compensation, but it can also be used to increase the soft-start time. soft start reduces surge currents from v in by gradually increasing the peak inductor current. power supply sequencing can also be accomplished using this pin. the ltc3568 has an a pplica t ions i n f or m a t ion
ltc3568 3568fa run r t shdn/r t (3a) (3b) (3c) run r t shdn/r t 1m sv in 3568 f03 run or v in i th c1 c c d1 r c r1 a pplica t ions i n f or m a t ion internal digital soft-start which steps up a clamp on i th over 1024 clock cycles, as can be seen in figure 4. the soft-start time can be increased by ramping the volt- age on i th during start-up as shown in figure 3(c). as the voltage on i th ramps through its operating range the internal peak current limit is also ramped at a proportional linear rate. to ground, pulse skipping operation is selected which provides the lowest output voltage and current ripple at the cost of low current efficiency. applying a voltage between sv in C 1v and 1v, results in forced continuous mode, which creates a fixed output ripple and is capable of sinking some current (about 1/2 i l ). since the switch- ing noise is constant in this mode, it is also the easiest to filter out. in many cases, the output voltage can be simply connected to the sync/mode pin, giving the forced con- tinuous mode, except at startup. the ltc3568 can also be synchronized to an external clock signal by the sync/mode pin. the internal oscillator fre- quency should be set to 20% lower than the external clock frequency to ensure adequate slope compensation, since slope compensation is derived from the internal oscillator. during synchronization, the mode is set to pulse skipping and the top switch turn on is synchronized to the rising edge of the external clock. checking transient response the opti-loop ? compensation allows the transient response to be optimized for a wide range of loads and output capacitors. the availability of the i th pin not only allows optimization of the control loop behavior but also provides a dc-coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the figure 1 circuit will provide an adequate starting point for most applica- tions. the series r-c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms figure 3. shdn/r t pin interfacing and external soft-start figure 4. digital soft-start v in = 3.3v v out = 2.5v i load = 1.8a v in 5v/div v out 1v/div i l 1a/div 400s/div 3568 f04 mode selection and frequency synchronization the sync/mode pin is a multipurpose pin which provides mode selection and frequency synchronization. connect- ing this pin to v in enables burst mode operation, which provides the best low current efficiency at the cost of a higher output voltage ripple. when this pin is connected
ltc3568 3568fa a pplica t ions i n f or m a t ion that will give a sense of the overall loop stability without breaking the feedback loop. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out im- mediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. the gain of the loop increases with r and the bandwidth of the loop increases with decreasing c. if r is increased by the same factor that c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. in addition, a feedforward capacitor c f can be added to improve the high frequency response, as shown in figure 5. capacitor c f provides phase lead by creating a high frequency zero with r2 which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to linear technology application note 76. although a buck regulator is capable of providing the full output current in dropout, it should be noted that as the input voltage v in drops toward v out , the load step capability does decrease due to the decreasing voltage across the inductor. applications that require large load step capabil- ity near dropout should use a different topology such as sepic, zeta or single inductor, positive buck/boost. in some applications, a more severe transient can be caused by switching in loads with large (>1uf) input capacitors. the discharged input capacitors are effectively put in paral- lel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of pv in ltc3568 pgood pgood sw sv in sync/mode v fb i th shdn/r t l1 v in 2.5v to 5.5v sgnd pgnd r5 c f r t r c r1 r2 3568 f05 c c c ith c5 v out c in + + c6 pgnd sgnd pgnd sgnd sgnd sgnd sgnd gnd pgnd pgnd c out r6 c8 sgnd figure 5. ltc3568 general schematic
ltc3568 3568fa a pplica t ions i n f or m a t ion the losses in ltc3568 circuits: 1) ltc3568 v in current, 2) switching losses, 3) i 2 r losses, 4) other losses. 1. the v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small loss that increases with v in , even at no load. 2. the switching current is the sum of the mosfet driver and control currents. the mosfet driver current re- sults from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc bias current. in continuous mode, i gatechg = f o (qt + qb), where qt and qb are the gate charges of the internal top and bottom mosfet switches. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 3. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, rl. in continuous mode, the average output current flowing through inductor l is chopped between the internal top and bottom switches. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on) top)(dc) + (r ds(on) bot)(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses: i 2 r losses = i out 2(r sw + rl) 4. other hidden losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching fre- quency. other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. thermal considerations in a majority of applications, the ltc3568 does not dis- sipate much heat due to its high efficiency. however, in applications where the ltc3568 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3568 from exceeding the maximum junc- tion temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t rise = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t rise + t ambient as an example, consider the case when the ltc3568 is in dropout at an input voltage of 3.3v with a load current of 1.8a with a 70c ambient temperature. from the typical performance characteristics graph of switch resistance, the r ds(on) resistance of the p - channel switch is 0.125 . therefore, power dissipated by the part is: p d = i 2 ? r ds(on) = 405mw the dfn package junction-to-ambient thermal resistance, ja is 43c/w. therefore, the junction temperature of the regulator operating in a 70c ambient temperature is approximately: t j = 0.405 ? 43 + 70 = 87.4c remembering that the above junction temperature is obtained from an r ds(on) at 70c, we might recalculate the junction temperature based on a higher r ds(on) since it increases with temperature. however, we can safely as- sume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125c.
ltc3568 3568fa a pplica t ions i n f or m a t ion design example as a design example, consider using the ltc3568 in a typical application with v in = 5v. the load requires a maximum of 1.8a in active mode and 10ma in standby mode. the output voltage is v out = 2.5v. since the load still needs power in standby, burst mode operation is selected for good low load efficiency. first, calculate the timing resistor: r mhz k t = ( ) = ? 9 78 10 1 323 8 11 1 08 . ? . . use a standard value of 324k. next, calculate the inductor value for about 40% ripple current at maximum v in : l v mhz ma v v h = ? ? ? ? ? ? ? = 2 5 1 720 1 2 5 5 1 7 . ? ? . . choosing the closest inductor from a vendor of 2h, results in a maximum ripple current of: = ? ? ? ? ? ? ? = i v mhz v v ma l 2 5 1 2 1 2 5 5 625 . ? ? . for cost reasons, a ceramic capacitor will be used. c out selection is then based on load step droop instead of esr requirements. for a 5% output droop: c a mhz v f out = 2 5 1 8 1 5 2 5 36 . . ? ( % ? . ) the closest standard value is 22f plus 10f. since the supplys output impedance is very low, c in is typically a 22f. in noisy environments, decoupling sv in from pv in with an r6/c8 filter of 1 /0.1f may help, but is typically not needed. the output voltage can now be programmed by choosing the values of r1 and r2. to maintain high efficiency, the current in these resistors should be kept small. choosing 2a with the 0.8v feedback voltage makes r1~400k. a close standard 1% resistor is 412k and r2 is then 887k. the compensation should be optimized for these compo- nents by examining the load step response but a good place to start for the ltc3568 is with a 13k and 1000pf filter. the output capacitor may need to be increased depending on the actual undershoot during a load step. the pgood pin is a common drain output and requires a pull-up resistor. a 100k resistor is used for adequate speed. figure 1 shows the complete schematic for this design example. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3568. these items are also illustrated graphically in the layout diagram of figure 6. check the following in your layout: figure 6. ltc3568 layout diagram (see board layout checklist) pv in ltc3568 pgnd sw sv in sgnd pgood pgood v fb sync/mode i th shdn/r t l1 v in bmps v in v out r5 r t r3 r1 r2 3568 f06 c3 bold lines indicate high current paths c in c out c4
ltc3568 3568fa a pplica t ions i n f or m a t ion 1. does the capacitor c in connect to the power v in (pin 6) and power gnd (pin 5) as close as possible? this capacitor provides the ac current to the internal power mosfets and their drivers. 2. are the c out and l1 closely connected? the (C) plate of c out returns current to pgnd and the (C) plate of c in . 3. the resistor divider, r1 and r2, must be connected between the (+) plate of c out and a ground line ter- minated near sgnd (pin 3). the feedback signal v fb should be routed away from noisy components and traces, such as the sw line (pin 4), and its trace should be minimized. 4. keep sensitive components away from the sw pin. the input capacitor c in , the compensation capacitor c c and c ith and all the resistors r1, r2, r t , and r c should be routed away from the sw trace and the inductor l1. 5. a ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the sgnd pin at one point which is then connected to the pgnd pin. 6. flood all unused areas on all layers with copper. flood- ing with copper will reduce the temperature rise of power components. these copper areas should be connected to one of the input supplies: pv in , pgnd, sv in or sgnd. sv in ltc3568 pgood pgood sw pv in sync/mode v fb i th shdn/r t sgnd l1 2h v in 2.5v to 5.5v v out 1.8v/2.5v/3.3v at 1.8a r5 100k r4 324k r1a 280k r3 13k rs1 1m bm rs2 1m 3568 f07a c3 1000pf c4 22pf r2 887k c2 22f x2 sgnd sgnd r1b 412k r1c 698k ps fc pgnd c1 22f pgnd pgnd sgnd note: in dropout, the output tracks the input voltage c1, c2: taiyo yuden jmk325bj226mm l1: toko a915ay-2rom (d53lc series) gnd 3.3v 2.5v 1.8v load current (ma) efficiency (%) 100 95 90 85 80 75 70 1 100 1000 10000 3568 f07b 10 v in = 3.3v v out = 2.5v circuit of figure 7 burst mode operation pulse skip forced continuous figure 7. general purpose buck regulator using ceramic capacitors efficiency vs load current typical a pplica t ions
ltc3568 3568fa typical a pplica t ions low output voltage, 2mm height buck regulator efficiency vs load current ps pv in ltc3568 pgood pgood sw sv in sync/mode v fb i th shdn/r t l1 1.7h v out 1.2v/1.5v/1.8v at 1.8a v in 2.5v to 5.5v sgnd pgnd sgnd gnd sgnd fc pgnd r5 100k c4 47pf r4 324k r3 13k r1c 787k r2 402k 3568 ta04 c3 1000pf c1 22f c1: taiyo yuden jmk325bj226mm c2: taiyo yuden jmk325bj476mm l1: sumida cdrh2d18/hp1r7 c2 47f x2 r1b 453k 1.2v 1.5v r1a 316k 1.8v r s1 1m r s2 1m bm load current (ma) efficiency (%) 95 90 85 80 75 70 1 100 1000 10000 3568 ta05 10 v in = 3.3v burst mode operation f o = 1mhz v out = 1.2v v out = 1.5v v out = 1.8v p ackage descrip t ion 3.00 p0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom view?exposed pad 1.65 p 0.10 (2 sides) 0.75 p0.05 r = 0.125 typ 2.38 p0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 p 0.05 2.38 p0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p0.05 (2 sides) 2.15 p0.05 0.50 bsc 0.70 p0.05 3.55 p0.05 package outline 0.25 p 0.05 0.50 bsc pin 1 notch r = 0.20 or 0.35 s 45o chamfer dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c)
ltc3568 3568fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 9/10 i-grade added. reflected throughout the data sheet 1 to 18
ltc3568 3568fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0910 rev a ? printed in usa pv in ltc3568 pgood pgood sw sv in sync/mode v fb i th shdn/r t l1 1h v out 1.8v at 1.8a v in 2.5v to 4.2v sgnd pgnd r5 100k c4 22pf r4 154k r3 10k r1 698k r2 887k 3568 ta02 c3 1000pf c7 47pf c1 10f x2 c1, c2: murata grm319r60j106ke01b l1: cooper sd10-1r0 c2 10f x3 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous step-down dc/dc converter 96% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20a, i sd <1a, thinsot? package ltc3407/ltc3407-2 dual 600ma/800ma (i out ), 1.5mhz/2.25mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd <1a, ms10e and dfn packages ltc3410/ltc3410b 300ma (i out ), 2.25mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 26a, i sd <1a, sc70 package ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 96% efficiency, v in : 2.6v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd <1a, ms10 and dfn packages ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 96% efficiency, v in : 2.6v to 5.5v, v out(min) = 0.8v, i q = 62a, i sd <1a, tssop-16e and qfn packages ltc3531/ltc3531-3/ ltc3531-3.3 200ma (i out ), 1.5mhz, synchronous buck-boost dc/dc converter 95% efficiency, v in : 1.8v to 5.5v, v out(min) : 2v to 5v, i q = 16a, i sd <1a, thinsot and dfn packages ltc3532 500ma (i out ), 2mhz, synchronous buck-boost dc/dc converter 95% efficiency, v in : 2.4v to 5.5v, v out(min) : 2.4v to 5.25v, i q = 35a, i sd <1a, ms10 and dfn packages ltc3542 500ma (i out ), 2.25mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 26a, i sd <1a, dfn package ltc3544 quad 300ma + 2x 200ma + 100ma 2.25mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 70a, i sd <1a, qfn package ltc3547/ltc3547b dual 300ma 2.25mhz, synchronous step-down dc/dc converter 96% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd <1a, dfn package ltc3548/ltc3548-1/ ltc3548-2 dual 400ma and 800ma (i out ), 2.25mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd <1a, ms10e and dfn packages ltc3560 800ma (i out ), 2.25mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 16a, i sd <1a, thinsot package 1mm height, 2mhz, li-ion to 1.8v converter efficiency vs load current load current (ma) efficiency (%) 95 65 90 85 80 75 70 60 1 100 1000 10000 3568 ta03 10 v out = 1.8v f o = 2mhz v in = 2.7v v in = 3.6v v in = 4.2v

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